Abstract— The ALU is a

one of most basic operational unit in any processor. The ALU is heart of any

system or any processor and the core component of the central processing unit

CPU because mainly all the basic operations are performed by the help of ALU

only. As the name ALU signifies arithmetic logic unit, hence it is used to

perform the arithmetic and logical operation in a digital bits. So the ALU can

be defined as the combinational unit which is used to perform its logical and arithmetic

units. The purpose of this work is to implement the Arithmetic Logic Unit (ALU)

by a CMOS technique in 45nm. The tasks perform by ALU are Logic operation (OR,

AND, XOR) and Arithmetic operation (ADDER). All the logical operations are

performed by the help of logic gates using GDI technology. The GDI is the most

commonly used technique for power reduction as it reduces the number of gates

used. This result is then given to the multiplexer and the result obtained is

dependent on the input select line. This result obtained is calculated is in

the term of average power and delay. The implementation takes place in a

software Cadence virtuoso.

Keywords— ALU

(Arithmatic and Logic Unit), CADENCE VIRTUOSO (Tool), CMOS(Complimentary Metal

Oxide Semiconductor), GDI Technique (Gate Diffusion Input)

I.

Introduction

The main part of any system is its

processor as the processor determines the speed of the processor. The ALU is

the heart of any processor as all the operation performed by the processor is

performed by the help of ALU only. Arithmetic and Logic Unit is one of the most

basic components of any computing machine. It has the capability of performing

various arithmetic and logical operations like addition, subtraction, AND, OR,

XOR etc., on given data and generating results. The number of operations it can

perform and the size of the data it can work with are dependent on the ALU.

With the increase in number of operation, the speed of an ALU is reduced so at

the design level there is need to increase the speed of a processor by the

proper choice of ALU operation depending upon application and type of circuit

to be implemented and designed. There are also various technique is present for

the power reduction of ALU in which GDI is also the one of them. Gate Diffused

Input technique is the technique reduces the number of transistor in circuit

due to which power reduces.

Now in modern computer processor are based on graphical

processing unit (GPU) it is combination of numbers of complex ALU and also ALU

are basic building blocks of Microprocessors, Digital Signal Processing (DSP),

Mobile and telecommunications, Laptops, wristwatches etc. The objective of this

paper is to present a modified low power ALU using GDI technique and to compare

that with the CMOS technique at 45nm

1.

II.

PREVIOUS

WORKS

Several

logic circuits have been implemented in various design styles. With rapid development of portable digital applications, the demand for

increasing speed, compact implementation, and low power dissipation. The wish

to improve the performance of logic circuits once based on traditional CMOS

technology, resulted in the development of many logic design techniques during

the last two .One form of logic that is popular in low-power digital circuits

is pass-transistor logic (PTL) 2.

Some of the main advantages of PTL over standard CMOS design are 1)

high speed, due to the small node capacitances; 2) low power dissipation, as a

result of the reduced number of transistors; and 3) lower interconnection

effects 3 due to a small area.

However, most of the PTL implementations

have two basic problems. First, the threshold drop across the single-channel

pass transistors results in reduced current drive and hence slower operation at

reduced supply voltages; this is particularly important for low-power design

since it is desirable to operate at the lowest possible voltage level. Second,

since the “high” input voltage level at the regenerative inverters is not, the

PMOS device in the inverter is not fully turned off, and hence direct-path

static power dissipation could be significant 4.

There are many sorts of PTL techniques

that intend to solve the problems mentioned above 5.

1) Transmission gate CMOS (TG) uses

transmission gate logic to realize complex logic functions using a small number

of complementary transistors. It solves the problem of low logic level swing by

using pMOS as well as nMOS 6.

2) Complementary pass-transistor logic

(CPL) features complementary inputs/outputs using nMOS pass-transistor logic

with CMOS output inverters. CPL’s most important feature is the small stack

height and the internal node low swing, which contribute to lowering the power

consumption. The CPL suffers from static power consumption due to the low swing

at the gates of the output inverters. To lower the power consumption of CPL

circuits, LCPL and SRPL circuit styles are used. Those styles contain pMOS

restoration transistors or cross-coupled inverters.

3) Double pass-transistor logic (DPL)

uses complementary transistors to keep full swing operation and reduce the dc

power consumption. This eliminates the need for restoration circuitry. One

disadvantage of DPL is the large area used due to the presence of pMOS

transistors.

An additional problem of existing PTL is

top-down logic design complexity, which prevents the pass transistors from

capturing a major role in real logic LSIs 7. One of the main reasons for this

is that no simple and universal cell library is available for PTL-based design.

A new method to get small area low power consumption and

high-speed for low power digital combinational circuit design known as Gate

Diffusion Input .The GDI approach allows implementation of a wide range of complex logic

functions using only two transistors. This method is suitable for design of

fast, low-power circuits, using a reduced number of transistors (as compared to

CMOS and existing PTL techniques), while improving logic level swing and static

power characteristics and allowing simple top-down design by using small cell

library2-3.

III.

GATE

DIFFUSION INPUT TECHNIQUE

Gate Diffusion Input – a new approach for low power digital combinational circuits this

approach allows reducing power consumptions, delay and area of the digital

circuits to maintain the low complexity of the logic design 2.

Gate diffusion

input technique allows implementation of a wide range of combinatorial

synchronous function using only two transistors. This method is found to be

suitable for design of fast,

low power circuits using only two transistors (as compared to CMOS and existing

PTL techniques), while simultaneously improving logic level swing and static

power characteristics and allows simple top down design methodology. The GDI

method is based on the use of simple cell as shown in Fig 1 At first glance the

basic cell resembles the standard CMOS inverter, but there are

important differences: GDI cell contain three inputs.-G (the common gate input

of the NMOS and PMOS transistors), P(input to the

outer diffusion node of the PMOS transistor) and N

(input

to the outer diffusion node of the NMOS transistor).The out node (the common

diffusion of both transistors)may be used as input or output port depending on

circuit structure8.

Fig 1 Gate Diffusion Input

TABLE I Functions

Implemented Using Basic GDI Cell

The main three basic gates used in this

work are given below by using GDI technique

A. AND GATE

AND Gate is one of the main block of the design. An AND gate is two

input, one output logic circuit, whose output assume logic 1 state when both

inputs assumes a logic 1 state. When both the input assumes the logic 0 state,

or when one and only one of its two inputs assumes a logic 1 state the output assumes a

logic 0 state. Fig 2 shows the implementation of AND gate using GDI techniques.

It uses less number of transistors as compared to conventional design of AND

Gate using CMOS logic units.

Fig

2 AND Gate

B. OR GATE

An OR gate is two input, one output logic circuit,

whose output assume logic 1 state when one and only one of its two inputs

assumes a logic 1 state and when both the input assumes the logic 1 state. When

both the input assumes the logic 0 state, the output assumes a logic 0 state.

Fig 3 shows the implementation of OR gate using GDI techniques. It can reduce

number of transistors than conventional design of OR Gate using CMOS logic units.

Fig 3 OR Gate

C. XOR GATE

XOR Gate is the main block of the design. An XOR gate is two input,

one output logic circuit, whose output assume logic 1 state when one and only

one of its two inputs assumes a logic 1 state. When both the input assumes the

logic 0 state, or when both the input assumes the logic 1 state the output

assumes logic 0 states. Fig 4 shows the implementation of XOR gate using GDI

techniques. It uses less number of transistors as compared to conventional

design of XOR Gate using CMOS logic units.

Fig 4 XOR Gate

TABLE II

Comparative Study of GDI and CMOS Schematics

The above, Table

II shows the comparative study between GDI and CMOS for different logic gates

showing their schematics.

IV.

ARITHMETIC

AND LOGICAL UNIT

Arithmetic Logic Unit (ALU) is

an integrated circuit within

a CPU or GPU that

performs arithmetic and logic operations. Arithmetic instructions include

addition, subtraction, and shifting operations, while logic instructions

include Boolean comparisons, such as AND, OR, XOR, and NOT operations. ALUs required in very large scale integrated circuits from

processors to application specific integrated circuits (ASICs).

Fig 5 GATE level diagram of Arithmetic and Logic Unit

Implemented a 2 Bit Arithmetic and logical unit. The major operation

performed by the ALU in this work is OR, AND, XOR and Addition. The main

features of this 2 Bit ALU are Low power technology, 1 arithmetic and 3 logical

operations, two select lines used to perform various operations at different

combinational input.

The major parts of proposed ALU are:-

Arithmetic Unit: – this unit provides an

arithmetic operation such as multiplier, addition and substation. In the

architecture a two bit adder is present with the carry.

Logical Unit: – this unit used to perform

logical operation with help of logic gates such as OR and XOR. This paper

present an OR, AND, XOR gate.

Multiplexer

Unit: – it a basic unit, which is used to defined that what operation is to

perform depending upon the select line. This paper used a four input

multiplexer which is formed by the combination of AND, OR gate 1.

The design of

2-bit ALU consists of two 4×1 multiplexers,

two full adders, two XOR gates, two AND

gates and two OR gates. All the logical and arithmetic operations are performed

by the help of logic gates using GDI

technology. This result is then given to the multiplexer and the result

obtained is dependent on the input select line.

TABLE III ALU Operations

S0

S1

FUNCTION

OPERATION

0

0

A?B

XOR

0

1

A

AND

1

0

A|B

OR

1

1

A+B

ADDITION

V.

SIMULATION RESULTS

Here the ALU is implemented and

simulated using a tool CADENCE VIRTUOSO in 45 nm technology. The results are in

terms of average power, number of transistors and delay.

Fig 6 Schematic of Arithmetic and Logic Unit

The above given is the schematic circuit of ALU here two select line

were used to select the operation to be performed the schematic is drown using

GDI basic cell due to which the area of chip is reduced.

The below is the waveform of a GDI cell in which output waveform vary

according to the select line and input value provided.

Fig 7 Waveform of ALU using GDI

The table below compares the average power, number of transistors and delay

in GDI and CMOS technique.

TABLE IV Analysis of 2 Bit ALU in CMOS and GDI

Sl.

No

Design

No.of Transistors

Average Power (mW)

Delay

(ps)

10-12

1

ALU With CMOS

168

36.27

92.53

2

ALU With GDI

80

06.15

0.306

The table below shows compare each blocks in ALU in GDI

and CMOS technique.

TABLE V Analysis of Different Blocks of ALU

Sl.

No

Design

Component

No.of Transistors

Average power

(uW)

1

CMOS

XOR

12

106.5

2

AND

6

3488

3

OR

6

1171

4

Full Adder

42

11396

1

GDI

XOR

4

9.624

2

AND

2

4.325

3

OR

2

4.273

4

Full Adder

14

4.195

VI.

CONCLUSION

In this paper, the comparison between CMOS and GDI Technique on 2

bit ALU take place and the above result conclude that the GDI technique is

better than CMOS technique. The topologies are realized using CADENCE VIRTUOSO

schematic tool. In any system design, the three main constraints which

determine the performance of the system are speed, area and power requirement

so the number of transistors, Power dissipation and propagation delay of ALU

were compared using CMOS and GDI techniques. GDI technique proved to have most excellent

result in terms of performance characteristics among all the design techniques.

Implementation of ALU by

using GDI technique can reduces number of transistor count so it is more area

efficient and also the power consumption and propagation delay decreases.

The Simulation shows that the ALU is implemented with less power that is 6mW

using GDI technique and this is very less as compared to 36mW (CMOS technology)

i.e. 60% of power reduction is achieved and delay of 0.306ps.

In

future, this work can be extended to higher bit and

more arithmetic and logic operations can be included.

ACKNOWLEDGMENT

I thank

Prof. Asha Panikar for her constructive comments and suggestions. Also thank

Jyothisree K.R the

staff of the Electronics

and Communication Department for their support during the work. Finally, I thank

the anonymous referees for their thorough review and useful comments references.